It is well known to convert an analog signal to digital form using a dual flash analog-to-digital converter, in which the analog signal is digitized in two successive conversion stages. The digital output of the first conversion stage is converted to analog form and is subtracted from the original analog signal, and the difference signal is applied to the second conversion stage. The desired digital signal is obtained by combining the outputs of the two conversion stages. The original analog signal is applied to the subtractor through a delay line to compensate for the propagation delay of the first conversion stage and of the digital-to-analog converter. It is necessary that the digital outputs of the two conversion stages represent the levels of the original analog signal and of the corresponding difference signal at the same point in time. This may be achieved by applying the analog signal to the converter through a sample and hold. However, conventional sample and holds degrade the analog signal to an extent that is unacceptable in some applications. The need for use of a sample and hold may be avoided by clocking the second conversion stage in delayed relation to the clocking of the first conversion stage, the delay of the clock signal being equal to the delay introduced by the delay line. The delays can be equalized either by adjusting the delay line or by adjusting the phase of the clock edge. Variable delay lines are generally more expensive than fixed delay lines, and it is difficult to adjust a variable delay line precisely.
Conventional high speed (&gt;10 MHz) circuits, such as high speed clock generators, do not have the accurate and stable voltage characteristics that are found in low frequency (&lt;10 kHz) circuits. One problem which arises from this limitation on conventional high speed circuits it that it is not possible, using such conventional circuits, to obtain precise control and adjustment of the phase of the clock edges of the clock signal generated by a high speed clock generator.